A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology

A 135mV 0.13W process tolerant 6T subthreshold DTMOS SRAM in 90nm technology" Abstract Cell stability and tolerance to process variation are of primary importance in subthreshold SRAMs. We propose a DTMOS based 6T SRAM suitable for subthreshold operation. For variation tolerant memory peripheral circuitry, we apply β-ratio modulation technique. DTMOS SRAM array fabricated in 90nm technology operates down to 135mV consuming 0.13µW at 750Hz. The proposed SRAM achieves 200% improvement in read static noise margin at iso-area compared to the conventional 6T SRAM at a supply voltage of 200mV. Introduction Efficient power management is becoming increasingly important with the rapid growth of portable, wireless, and battery operated applications, such as laptop computers, personal digital assistants (PDAs), and portable communication devices. One of the promising approaches to achieve ul-tralow power dissipation in such applications is to use sub-threshold (sub-V T) logic [1][2]. In sub-V T logic, circuits operate with a supply voltage (V dd) lower than the transistor threshold voltage (V T) and utilize the subthreshold leakage current as the operating current.